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Zynq7000 PS_PL Ethernet
by Max89 on Feb 8, 2021 |
Max89
Posts: 1 Joined: Jan 11, 2021 Last seen: Mar 3, 2021 |
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Hello everybody! I have a problem like this, I have an ALINX ax7015 debug board with two network interfaces. I know that one of them is connected to the processor (PS) and the other to the FPGA (PL). Tell me how can I create Block Design using Xilinx Vivado 2019 to connect both network interfaces? FPGA zynq7015-clg485-2
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